Field
The present disclosure relates generally to a standard cell architecture, and more particularly, to a metal oxide semiconductor (MOS) cell device architecture with mixed diffusion break isolation trenches.
Background
A standard cell device is an integrated circuit (IC) that implements digital logic.
An application-specific IC (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cell devices. A typical IC includes a stack of sequentially formed layers. Each layer may be stacked or overlaid on a prior layer and patterned to form the shapes that define transistors (e.g., field effect transistors (FETs) and/or a fin FETs (FinFETs)) and connect the transistors into circuits.
A diffusion break is a feature of a process technology that may be used to electrically isolate transistor regions within a standard cell device and/or to electrically isolate adjacent standard cell devices from each other. For example, a diffusion break may include a trench formed in the silicon substrate that isolates transistor regions within a standard cell device or isolates adjacent standard cell devices. However, conventional standard cell device architectures that include diffusion breaks often suffer from area penalties and/or standard cell device output penalties.
Accordingly, there is an unmet need for a diffusion break configuration that provides both efficient use of area and that has an improved standard cell device output.